1. Field of the Invention
The present invention generally relates to the manufacture of very large scale integrated (VLSI) circuits and, more particularly, to the resolution enhancement of photolithographic images through the use of phase shifted masks. More specifically, a method is provided to eliminate the most frequent type of design conflict in phase edge phase shifted masks.
2. Description of the Related Art
A very large scale integrated (VLSI) complementary metal oxide semiconductor (CMOS) chip is manufactured on a silicon wafer by a sequence of material additions (i.e., low pressure chemical vapor depositions, sputtering operations, etc.), material removals (i.e., wet etches, reactive ion etches, etc.), and material modifications (i.e., oxidations, ion implants, etc.). These physical and chemical operations interact with the entire wafer. For example, if a wafer is placed into an acid bath, the entire surface of the wafer will be etched away. In order to build very small electrically active devices on the wafer, the impact of these operations has to be confined to small, well defined regions.
Lithography in the context of VLSI manufacturing of CMOS devices is the process of patterning openings in photosensitive polymers (sometimes referred to as photoresists or resists) which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps. The manufacturing of CMOS chips involves the repeated patterning of photoresist, followed by an etch, implant, deposition, or other operation, and ending in the removal of the expended photoresist to make way for a new resist to be applied for another iteration of this process sequence.
The basic lithography system consists of a light source, a stencil or photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. Since a wafer containing from fifty to one hundred chips is patterned in steps of one to four chips at a time, these lithography tools are commonly referred to as steppers. The resolution of an optical projection system such as a lithography stepper is limited by parameters described in Rayleigh's equation: EQU R=k.sub.1 .lambda./NA, (1)
where .lambda. is the wavelength (in .mu.m) of the light source used in the projection system and NA is the numerical aperture of the projection optics used. k.sub.1 is a factor describing how well a combined lithography system can utilize the theoretical resolution limit in practice and it can range from 0.8 down to 0.5 for standard exposure systems. R is the resolution value for the optical projection system. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) steppers operating at 248 nm wavelengths but mid ultra violet (MUV) steppers with a wavelength of 356 nm are also in widespread use.
Conventional photomasks consists of chromium patterns on a quartz plate, allowing light to pass wherever the chromium is removed from the mask. Light of a specific wavelength is projected through the mask onto the photoresist coated wafer, exposing the resist wherever hole patterns are placed on the mask. Exposing the resist to light of the appropriate wavelength causes modifications in the molecular structure of the resist polymers which allows developer to dissolve and remove the resist in the exposed areas. Negative resist systems allow only unexposed resist to be developed away. The photomask, when illuminated, can be pictured as an array of individual, infinitely small light sources which can be either turned on (points in clear areas) or turned off (points covered by chrome). If the amplitude of the electric field vector which describes the light radiated by these individual light sources is mapped across a cross section of the mask, a step function will be plotted reflecting the two possible states that each point on the mask can be found in (light on, light off).
These conventional photomasks are commonly referred to as chrome on glass (COG) binary masks, due to the binary nature of the image amplitude. The perfectly square step function exists only in the theoretical limit of the exact mask plane. At any distance away from the mask, such as in the wafer plane, diffraction effects will cause images to exhibit a finite image slope. At small dimensions, that is, when the size and spacing of the images to be printed are small relative to the .lambda./NA (NA being the numerical aperture of the exposure system), electric field vectors of adjacent images will interact and add constructively. The resulting light intensity curve between the features is not completely dark, but exhibits significant amounts of light intensity created by the interaction of adjacent features. The resolution of an exposure system is limited by the contrast of the projected image, that is the intensity difference between adjacent light and dark features. An increase in the light intensity in nominally dark regions will eventually cause adjacent features to print as one combined structure rather than discrete images.
The quality with which small images can be replicated in lithography depends largely on the available process latitude; that is, the amount of allowable dose and focus variation that still results in correct image size. Phase shifted mask (PSM) lithography improves the lithographic process latitude or allows operation of a lower k.sub.1 value (see equation 1) by introducing a third parameter on the mask. The electric field vector, like any vector quantity, has a magnitude and direction, so in addition to turning the electric field amplitude on and off, it can be turned on with a 0.degree. phase or turned on with a 180.degree. phase. This phase variation is achieved in PSMs by modifying the length that a light beam travels through the mask material. By recessing the mask by the appropriate depth, light traversing the thinner portion of the mask and light traversing the thicker portion of the mask will be 180.degree. out of phase; that is, their electric field vectors will be of equal magnitude but point in exactly opposite directions so that any interaction between these light beams results in perfect cancellation. For more information on PSM, the reader is referred to "Phase-Shifting Mask Strategies: Isolated Dark Lines", Marc D. Levenson, Microlithography World, March/April 1992, pp. 6-12.
The limits of PSM lithography can be uniquely challenged by the manufacture of high-performance logic derivatives of advanced Dynamic Random Access Memory (DRAM) technologies. These technologies are entering development cycles with immediate requirements for sub-quarter micron printed gate lengths and tight dimensional control on the gate structures across large chip areas. Since these logic technologies are based on shrinking the gate length in an established DRAM technology, the overall layout pitch remains constant for all critical mask levels, resulting in narrow, optically isolated lines on the scaled gate level. The requirement for tight line width control on narrow isolated lines drives the requirement of phase edge PSMs for these logic applications.
Phase edge PSM lithography makes use of contrast enhancement caused by a phase transition under an opaque feature on a mask. This phase transition is achieved by etching an appropriate depth into the quartz mask substrate on one side of a narrow line structure on the mask. Not all narrow line structures on the mask close upon themselves, some edges of the etched region will terminate in bare quartz regions. Since the 180.degree. phase transition forces a minimum in the image intensity, narrow dark lines will be printed by these excess phase edges. Currently, the unwanted images are erased using a trim mask, a second mask that transmits light only in regions left unexposed by the residual phase edge.
Even though resolution enhancement through the use of hard phase shifted masks (frequency doubling masks) has been extensively proven, implementation of this technique is critically dependent on computer assisted design (CAD) technology that can modify existing circuit designs to incorporate the additional design levels needed to build a phase shifted mask. Design modifications consist of defining regions on the mask that require phase shifting (i.e., by etching into the mask substrate) relative to the rest of the mask, and of designs added to eliminate lines printed by unwanted phase edges. The basic concept of creating a phase transition across any small feature is easily realized and can be done, given sufficient time, on a graphics terminal by hand. The challenge that needs to be met before introducing hard phase shifters to VLSI product programs lies in the rapid, reliable design modifications of complex chip designs. No manufacturable CAD system exists that can efficiently translate phase shift design rules into regions that need phase assignment, as is necessary for all light field design levels such as the gate level, typically one of the most critical levels for line width control.
It is well known to those skilled in the art of phase edge lithography that three way intersections at minimum dimension cannot be phase shifted; i.e., the three rectangular shapes forming the background behind three lines, all at a width narrow enough to require phase shifting, join at a common node and cannot be colored with only two colors while requiring a color change across each segment of the intersection.
Unfortunately, many widely used basic CMOS circuit components, such as inverters, require a poly wire to run from one input of two MOSFETs, thereby creating a three way intersection. Fortunately, the resulting three way intersection occurs in poly wiring, not in active poly gates, allowing slight modifications in the design to avoid the conflict in the phase assignment without impacting the circuit performance.
Two design modifications, both targeted at eliminating the three way intersection at minimum dimension, are possible. First, the three way intersection can be turned into a four way intersection with one sacrificial leg that will be eliminated in the trim process. Second, the three way intersection can be converted into a two way intersection by widening one leg to the point where phase shifting is no longer required. The first technique is usually less desirable due to space constraints. The second technique works well but is extremely time consuming if implemented manually in an existing design. Changing design rules to force the widened leg in three way intersections from the start would seriously impede the migration of existing designs and design libraries to ground rules where phase edge PSM is necessary.
The present invention relates to the automatic elimination of three way, or "T", intersections in the original CAD layout.